In the post-Moore era, how can advanced packaging achieve a magnificent turn? The three major companies led by TSMC have expanded their recruitment

Recently, Intel Chief Executive Pat Gelsinger said that the growth of the semiconductor industry will welcome "10 years of prosperity." The new product launch conference of old rival AMD and the evolution of semiconductor packaging triggered by 3D Chiplet are also impressive. Wu Hanming, the academician of the Chinese Academy of Engineering and dean of the School of Micro-Nanoelectronics, Zhejiang University, emphasized that in the development process of the post-Moore era, high-performance computing, mobile computing, and autonomous perception are the three major driving forces, and these three major drivers lead the eighth technology research and development. Main content: They are logic technology, basic rule scaling, performance-power-size (PPA) scaling, 3D integration, memory technology, DRAM technology, Flash technology, and emerging non-volatile memory technology. The goal to be achieved under the three major driving forces is that PPAC (performance, power, area, cost) will have a certain improvement in 2-3 years, and the range of improvement will be between 15%-30%.

Coincidentally, in June, at the Taipei Computer Show, AMD President and CEO Dr. Su Zifeng demonstrated the new 3D chipset technology, which will lead to the breakthrough of high-performance computing cutting-edge technology. AMD is working with TSMC to develop the first chip to use 3D vertical cache. Dr. Su took a chip developed by Ryzen 5900X as a prototype to demonstrate the preliminary results of this technology.

3D stacking technology has been used in flash memory for a long time. Today AMD brings this technology to the CPU. It breaks through the combination of AMD chip architecture with 3D stacking technology, which can increase the interconnect density of 2D chips by more than 200 times, compared with the existing 3D packaging. The solution density can reach more than 15 times.

This is the prototype design of the Ryzen 5900X processor using 3D stacking technology. On the left chip, there is a 6mm*6mm square SRAM combined with CCD. It is on a 12-core or 16-core Ryzen processor with dual CCDs. It has a total of 192MB of L3 cache. After adding the 3D vertical cache, the 12-core Zen 3 Ryzen processor has increased the average frame rate of "Gears of War 5" by 12% at the same frequency, and the overall game performance has increased by 15%.

What is the magic of 3D Chiplet packaging technology? Why was this packaging technology born? What is the latest development? The author gathers the latest views and product developments of star companies in the field of chip foundry and chip packaging such as TSMC, ASE, Changjiang Electronics Technology, etc., and conducts in-depth analysis with you.

The 3D IC era is accelerating, and TSMC plans to officially open its 3DFabric dedicated wafer fab in 2022

At the 2021 Technology Forum held recently, TSMC CEO Wei Jiazhe lamented that the global digital transformation in 2021 will be carried out at an astonishing speed. Offices, education, and entertainment will require a lot of high-speed computing. The epidemic has made more people around the world aware of the impact of semiconductors on the global economy. The importance of.

Wei Jiazhe said that 2D scaling is no longer sufficient to support system integration needs. Due to TSMC's forward-looking investment and R&D efforts, 3DIC technology is already a viable path, while meeting the needs of system efficiency, reduction in area, and integration of different functions.

Behind the 3D chipset released by AMD is TSMC's advanced semiconductor process technology and advanced packaging technology. In this years ISSCC, TSMC demonstrated the SOIC technology. This time TSMC named the technology for commercial use (3DFabric) and announced data related to interconnection density. Compared with the traditional bump-based 3DIC technology, the interconnection density can be increased by 16 times. This data is also roughly in line with the relevant figures released by AMD at Computex this time (compared to 3DIC interconnect density increased by 15 times). TSMC believes that in addition to the advancement of high-computing power chips in advanced manufacturing processes, advanced packaging technology is the key to further expansion of density, and 3D packaging technology is the best way to move forward. Currently, TSMC's 3D IC technology includes Cowos, InFO, and SoIC.

Zhang Xiaoqiang, senior vice president of business development at TSMC, pointed out that InFO_B packaging technology is a new technology of the InFO series. Based on InFO_PoP's years of mass production experience, it can effectively increase the chip size of the packaging, which is very important for mobile phone products. Especially for 5G mobile platforms, TSMC has InFO POP for mobile applications, InFO Antenna-in-package (InFO_AiP) for RF front-end module (FEM) applications, and multi-stack (MUST) for RF front-end module (MUST) ), baseband modem.

The characteristics of InFO_oS packaging technology, considering the packaging technology mainly for HPC applications, use InFO to integrate different logic chips so that the InFO capability can be increased from one reticle to 2.5 reticle size, which can integrate more and larger chips on one module. , This has a very positive effect on future HPC applications.

In addition, TSMC has also developed the industry's first high-density chip stacking technology. It has developed two different technologies, Chip-on-wafer, and wafer-on-wafer, which can stack heterogeneous chips and homogeneous chips, greatly improving System efficiency, reduce product size.

ASE launched wafer-level FOWLP technology

Recently, at the Nanjing Semiconductor Conference, Guo Guiguan, deputy general manager of ASE Group, pointed out that with the increasing complexity of chips, testing is more time-consuming and labor-intensive, and the use of different packaging technologies for heterogeneous chip integration is the development trend of the new era.

In Guo Guiguan's view, wafer cost and yield have been the focus of the industry. "If we all pursue 3nm and 5nm, the cost in terms of yield is extremely high. If Chiplet does not need to be assembled into a very large chip, it can be discretely divided into several small chips for integration, the yield rate will be greatly improved. ."

"I think that in addition to SOC single-chips, 2.5D or even combined with 2.5D and 3D high-performance computing chips, SIP will also bring out the need for heterogeneous system integration. In September, you will see more products have been applied to The fan-out type is the concept of the two-layer SIP." Guo Guiguan said that the author also saw ASE brought 2.5D and 3D packaged products at the booth.

What opportunities does 5G bring to packaging factories? Guo Guiguan believes that 5G is not only fast transmission but also high-performance technology. This part has a faster response speed. We define it as HPC. ASE has two obvious trends for SIP packaging: First, the thickness will increase from single-sided to double-sided, and the increase in thickness far exceeds practical applications. The thickness of the apple is 0.75, and the thickness of the mobile phone cases in this room is far more than that. This part has been shrinking over time on the one hand; on the other hand, it has begun to add a lot of special-shaped keys, which can be contact pieces connected to the external antenna. The advantage is that there is no need to rely on the substrate. Another advantage is that the line width and spacing are more optimized.

ASE has launched the wafer-level FOWLP (Fan-out Wafer-Level Package) technology, and the panel-level FOPLP (Fan-out Panel-Level Package) has been launched by ASE, Licheng, Samsung, etc. The competition is fierce.

Two core technologies of Changjiang Electronics Technology realize heterogeneous integration

Zheng Li, vice chairman of the China Semiconductor Industry Association, director and chief executive officer of Changjiang Electronics Technology, said: "The manufacturing technology and value of finished semiconductor devices in the post-Moore era far exceed the scope of packaging and testing. The current industry upgrades trend from advanced packaging to finished chip manufacturing Obviously, the two core technologies of Changjiang Electronics can achieve heterogeneous integration. At the same time, it is very important to coordinate design to optimize the integration of finished chip integration and testing."

The 2.5D Chiplet, 3D Chiplet, and other heterogeneous integrations shown by AMD at the Taipei Computer Show last week have increased the density by 300 times. TSMC, Intel, and leading international semiconductor companies are actively deploying semiconductor heterogeneous integration applications.

Subversive breakthroughs are taking place in advanced chip manufacturing technology, and Changjiang Electronics Technology is also constantly shifting gears and speeding up on the heterogeneous integration technology track. For Chiplet heterogeneous integration applications, Changjiang Electronics Technology has launched a full range of XDFO solutions, including 2D Chiplet, 2.5D Chiplet, and 3D Chiplet, which can be applied to applications such as mobile communications, automotive, medical, and artificial intelligence.

Based on design requirements, Changdian Technology's through-silicon via fan-out wafer-level high-density packaging technology can use stacked via technology (Stacked VIA) in the silicon interposer (Si Interposer) instead of through silicon via technology (TSV). This technology can realize multi-layer RDL rewiring layers, 2×2um line width spacing, 40um extremely narrow bump interconnection, multi-layer chip stacking, integration of high-bandwidth storage, and integration of passive components.

Changjiang Electronics Technology has accumulated nearly 10 years of fan-out technology. Combining high-density SIP technology, it has launched a 2.5D chipset, 3D chiplet, and other product solutions for the future, which can flexibly realize heterogeneous integration. Zheng Li revealed that these products will have projects and solutions for face-to-face production in 2022 and 2023.

Zheng Li emphasized: "In addition to continuous breakthroughs in technology and process, to achieve low-cost, high-performance, environmentally friendly and high-quality integrated circuit product manufacturing, system-level electrical performance, structure, thermal simulation and system design are also required. This makes the integration of chip product integration testing a trend. Changjiang Electronics Technology will cooperate with IP, design companies, and EDA companies, and the collaborative design of the main body of the chip will be done."

summary

Academician Mao Junfa, the academician of the Chinese Academy of Sciences, pointed out that heterogeneous integrated circuits have outstanding characteristics: first, they can integrate the advantages of different semiconductor materials, processes, structures, and components or chips; second, adopt system design concepts; third, apply advanced technologies such as IP and small chips Chiplet; has a 2.5D or 3D high-density structure. The advantages of heterogeneous integrated circuits are obvious: First, it achieves powerful complex functions, excellent comprehensive performance, and breaks the performance limit of a single semiconductor process; second, flexibility, high reliability, and short development cycle; third, three-dimensional integration can achieve miniaturization, Lightweight; relatively low requirements for semiconductor equipment, not restricted by EUV lithography machine.

The latest practices and technological evolutions of TSMC, ASE, and Changjiang Electronics Technology are believed to bring more help to the implementation of 5G high-performance computing, AI, and IoT chips in the future, and it is also one of the possible paths for China's chip to overtake on a curve.

Recently, Intel Chief Executive Pat Gelsinger said that the growth of the semiconductor industry will welcome "10 years of prosperity." The new product launch conference of old rival AMD and the evolution of semiconductor packaging triggered by 3D Chiplet are also impressive. Wu Hanming, the academician of the Chinese Academy of Engineering and dean of the School of Micro-Nanoelectronics, Zhejiang University, emphasized that in the development process of the post-Moore era, high-performance computing, mobile computing, and autonomous perception are the three major driving forces, and these three major drivers lead the eighth technology research and development. Main content: They are logic technology, basic rule scaling, performance-power-size (PPA) scaling, 3D integration, memory technology, DRAM technology, Flash technology, and emerging non-volatile memory technology. The goal to be achieved under the three major driving forces is that PPAC (performance, power, area, cost) will have a certain improvement in 2-3 years, and the range of improvement will be between 15%-30%.

Coincidentally, in June, at the Taipei Computer Show, AMD President and CEO Dr. Su Zifeng demonstrated the new 3D chiplet technology, which will lead to the breakthrough of high-performance computing cutting-edge technology. AMD is working with TSMC to develop the first chip to use 3D vertical cache. Dr. Su took a chip developed by Ryzen 5900X as a prototype to demonstrate the preliminary results of this technology.

3D stacking technology has been used in flash memory for a long time. Today AMD brings this technology to the CPU. It breaks through the combination of AMD chip architecture with 3D stacking technology, which can increase the interconnect density of 2D chips by more than 200 times, compared with the existing 3D packaging. The solution density can reach more than 15 times.

This is the prototype design of the Ryzen 5900X processor using 3D stacking technology. On the left chip, there is a 6mm*6mm square SRAM combined with CCD. It is on a 12-core or 16-core Ryzen processor with dual CCDs. It has a total of 192MB of L3 cache. After adding the 3D vertical cache, the 12-core Zen 3 Ryzen processor has increased the average frame rate of "Gears of War 5" by 12% at the same frequency, and the overall game performance has increased by 15%.

What is the magic of 3D Chiplet packaging technology? Why was this packaging technology born? What is the latest development? The author gathers the latest views and product developments of star companies in the field of chip foundry and chip packaging such as TSMC, ASE, Changjiang Electronics Technology, etc., and conducts in-depth analysis with you.

The 3D IC era is accelerating, and TSMC plans to officially open its 3DFabric dedicated wafer fab in 2022

At the 2021 Technology Forum held recently, TSMC CEO Wei Jiazhe lamented that the global digital transformation in 2021 will be carried out at an astonishing speed. Offices, education, and entertainment will require a lot of high-speed computing. The epidemic has made more people around the world aware of the impact of semiconductors on the global economy. The importance of.

Wei Jiazhe said that 2D scaling is no longer sufficient to support system integration needs. Due to TSMC's forward-looking investment and R&D efforts, 3DIC technology is already a viable path, while meeting the needs of system efficiency, reduction in area, and integration of different functions.

Behind the 3D chiplet released by AMD is TSMC's advanced semiconductor process technology and advanced packaging technology. In this years ISSCC, TSMC demonstrated the SOIC technology. This time TSMC named the technology for commercial use (3DFabric) and announced data related to interconnection density. Compared with the traditional bump-based 3DIC technology, the interconnection density can be increased by 16 times. This data is also roughly in line with the relevant figures released by AMD at Computex this time (compared to 3DIC interconnect density increased by 15 times). TSMC believes that in addition to the advancement of high-computing power chips in advanced manufacturing processes, advanced packaging technology is the key to further expansion of density, and 3D packaging technology is the best way to move forward. Currently, TSMC's 3D IC technology includes Cowos, InFO, and SoIC.

Zhang Xiaoqiang, senior vice president of business development at TSMC, pointed out that InFO_B packaging technology is a new technology of the InFO series. Based on InFO_PoP's years of mass production experience, it can effectively increase the chip size of the packaging, which is very important for mobile phone products. Especially for 5G mobile platforms, TSMC has InFO POP for mobile applications, InFO Antenna-in-package (InFO_AiP) for RF front-end module (FEM) applications, and multi-stack for RF front-end module (MUST)Stack (MUST), baseband modem.

The characteristics of InFO_oS packaging technology, considering the packaging technology mainly for HPC applications, use InFO to integrate different logic chips so that the InFO capability can be increased from one reticle to 2.5 reticle size, which can integrate more and larger chips on one module. , This has a very positive effect on future HPC applications.

In addition, TSMC has also developed the industry's first high-density chip stacking technology. It has developed two different technologies, Chip-on-wafer, and wafer-on-wafer, which can stack heterogeneous chips and homogeneous chips, greatly improving System efficiency, reduce product size.

ASE launched wafer-level FOWLP technology

Recently, at the Nanjing Semiconductor Conference, Guo Guiguan, deputy general manager of ASE Group, pointed out that with the increasing complexity of chips, testing is more time-consuming and labor-intensive, and the use of different packaging technologies for heterogeneous chip integration is the development trend of the new era.

In Guo Guiguan's view, wafer cost and yield have been the focus of the industry. "If we all pursue 3nm and 5nm, the cost in terms of yield is extremely high. If Chiplet does not need to be assembled into a very large chip, it can be discretely divided into several small chips for integration, the yield rate will be greatly improved. ."

"I think that in addition to SOC single-chips, 2.5D or even combined with 2.5D and 3D high-performance computing chips, SIP will also bring out the need for heterogeneous system integration. In September, you will see more products have been applied to The fan-out type is the concept of the two-layer SIP." Guo Guiguan said that the author also saw ASE brought 2.5D and 3D packaged products at the booth.

What opportunities does 5G bring to packaging factories? Guo Guiguan believes that 5G is not only fast transmission but also high-performance technology. This part has a faster response speed. We define it as HPC. ASE has two obvious trends for SIP packaging: First, the thickness will increase from single-sided to double-sided, and the increase in thickness far exceeds practical applications. The thickness of the apple is 0.75, and the thickness of the mobile phone cases in this room is far more than that. This part has been shrinking over time on the one hand; on the other hand, it has begun to add a lot of special-shaped keys, which can be contact pieces connected to the external antenna. The advantage is that there is no need to rely on the substrate. Another advantage is that the line width and spacing are more optimized.

ASE has launched the wafer-level FOWLP (Fan-out Wafer-Level Package) technology, and the panel-level FOPLP (Fan-out Panel-Level Package) has been launched by ASE, Licheng, Samsung, etc. The competition is fierce.

Two core technologies of Changjiang Electronics Technology realize heterogeneous integration

Zheng Li, vice chairman of the China Semiconductor Industry Association, director and chief executive officer of Changjiang Electronics Technology, said: "The manufacturing technology and value of finished semiconductor devices in the post-Moore era far exceed the scope of packaging and testing. The current industry upgrades trend from advanced packaging to finished chip manufacturing Obviously, the two core technologies of Changjiang Electronics can achieve heterogeneous integration. At the same time, it is very important to coordinate design to optimize the integration of finished chip integration and testing."

The 2.5D Chiplet, 3D Chiplet, and other heterogeneous integrations shown by AMD at the Taipei Computer Show last week have increased the density by 300 times. TSMC, Intel, and leading international semiconductor companies are actively deploying semiconductor heterogeneous integration applications.

Subversive breakthroughs are taking place in advanced chip manufacturing technology, and Changjiang Electronics Technology is also constantly shifting gears and speeding up on the heterogeneous integration technology track. For Chiplet heterogeneous integration applications, Changjiang Electronics Technology has launched a full range of XDFO solutions, including 2D Chiplet, 2.5D Chiplet, and 3D Chiplet, which can be applied to applications such as mobile communications, automotive, medical, and artificial intelligence.

Based on design requirements, Changdian Technology's through-silicon via fan-out wafer-level high-density packaging technology can use stacked via technology (Stacked VIA) in the silicon interposer (Si Interposer) instead of through silicon via technology (TSV). This technology can realize multi-layer RDL rewiring layers, 2×2um line width spacing, 40um extremely narrow bump interconnection, multi-layer chip stacking, integration of high-bandwidth storage, and integration of passive components.

Changjiang Electronics Technology has accumulated nearly 10 years of fan-out technology. Combining high-density SIP technology, it has launched 2.5D chiplet, 3D chiplet, and other product solutions for the future, which can flexibly realize heterogeneous integration. Zheng Li revealed that these products will have projects and solutions for face-to-face production in 2022 and 2023.

Zheng Li emphasized: "In addition to continuous breakthroughs in technology and process, to achieve low-cost, high-performance, environmentally friendly and high-quality integrated circuit product manufacturing, system-level electrical performance, structure, thermal simulation and system design are also required. This makes the integration of chip product integration testing a trend. Changjiang Electronics Technology will cooperate with IP, design companies, and EDA companies, and the collaborative design of the main body of the chip will be done."

summary

Academician Mao Junfa, academician of the Chinese Academy of Sciences, pointed out that heterogeneous integrated circuits have outstanding characteristics: first, they can integrate the advantages of different semiconductor materials, processes, structures, and components or chips; second, adopt system design concepts; third, apply advanced technologies such as IP and small chips Chiplet; has a 2.5D or 3D high-density structure. The advantages of heterogeneous integrated circuits are obvious: First, it achieves powerful complex functions, excellent comprehensive performance, and breaks the performance limit of a single semiconductor process; second, flexibility, high reliability, and short development cycle; third, three-dimensional integration can achieve miniaturization, Lightweight; relatively low requirements for semiconductor equipment, not restricted by EUV lithography machine.

The latest practices and technological evolutions of TSMC, ASE, and Changjiang Electronics Technology are believed to bring more help to the implementation of 5G high-performance computing, AI, and IoT chips in the future, and it is also one of the possible paths for China's chip to overtake on a curve.